Semiconductor manufacturing apparatus detecting state of connection between controllers

ABSTRACT

An interlock system can discriminate a controller in which an abnormality occurs in a control system of a semiconductor manufacturing apparatus in which a plurality of controllers are connected through a network. A processing system contains at least one processing chamber which performs a semiconductor manufacturing process. A conveyance system takes an object to be processed in and out of the processing chamber. The control system includes at least one apparatus controller, which controls the processing system and the conveyance system, and an equipment controller, which manages the apparatus controller. The apparatus controller and the equipment controller are communicably connected through a network. The apparatus controller and the equipment controller are also connected via a hard wire so as to transmit a status signal of the apparatus controller and the equipment controller to the control system so that a presence of each apparatus controller and a status of connection between the controllers can be detected without using communication through the network.

TECHNICAL FIELD

[0001] The present invention relates to a controller connected via anetwork and, more particularly, to a method of detecting a connectionstate between controllers of a multi-chamber system in a semiconductormanufacturing apparatus and a semiconductor manufacturing apparatusperforming such a method.

BACKGROUND ART

[0002] Generally, a semiconductor manufacturing apparatus is providedwith various processing chambers that carry out each process tomanufacture a semiconductor device in combination. A conveyancemechanism which carries wafers is provided between processing chambersand between a cassette accommodating many wafers and the processingchambers. An apparatus controller is provided to a plurality ofprocessing chambers and conveyance mechanisms so that a desiredoperation is performed according to the order specification of asemiconductor manufacturing apparatus or the purpose of the user's use.

[0003] The multi-chamber semiconductor manufacturing apparatus includinga plurality of processing chambers and conveyance mechanism is providedwith a plurality of apparatus controllers or a plurality of CPUs forcontrol. In this case, it is desired to comprehensively control eachapparatus controller so as to achieve a complicated work safely,reliably and efficiently. Then, a tightly-coupled type control system ofa type, which carries out a bus connection of apparatus controllers tocarry out an intensive control, is developed.

[0004] However, when the bus connection of each equipment controller iscarried out, it is difficult to carry out a maintenance check of theapparatus controllers on an individual basis. Additionally, eachapparatus controller and a corresponding processing chamber cannot beoperated alone. Furthermore, it is difficult to detach the processingchambers freely.

[0005] Accordingly, in order to reduce a system down time, aloosely-coupled type control system has been developed in whichapparatus controllers are connected via a network such as the Ethernetso that an individual maintenance and an individual control can beperformed. The loosely-coupled type control system is provided with anequipment controller as an upper order controller with respect to theapparatus controller. The equipment controller generally controls thewhole semiconductor manufacturing apparatus. In such a loosely-coupledtype control system, communication between controllers is performedaccording to a communication protocol used in the network. Programs,parameter data, control information, etc. for operating the processingchambers and conveyance mechanism are transferred via a network.

[0006] When communicating between controllers via a network as mentionedabove, it takes a time of an order of several seconds to several tens ofseconds is needed (it is dependent on a design) until one controllerchecks whether a communication connection has been established betweenthe other controller. Additionally, it is impossible fro one controllerto distinguish whether the other controller is down or a malfunctionoccurs in the network when the communication connection cannot beestablished. Furthermore, an abnormal state of the controller cannot bechecked unless it goes through the network. Moreover, it is alsodifficult to distinguish a case where the controller is not connectedfrom a case where the controller is out of order.

[0007] Therefore, when a abnormality occurs in a certain controller oran abnormalities occurs in a network in the conventional control systemof the semiconductor manufacturing apparatus in which a plurality ofcontrollers are connected through the network, a time of an order ofseveral seconds to several tens of seconds passes until one controllerrecognizes an occurrence of an abnormality in a remote controller or anetwork, that is, until it is determined that the communicationconnection cannot be established. However, other process chambers or theconveyance mechanism continue to perform regular operations during thetime for determining the establishment of the communication connection,when the worst, an unexpected problem may occur in a worst case.Moreover, since it cannot specify whether the generation source of theabnormalities is a network or a controller, a trouble may occur inrestoration.

DISCLOSURE OF INVENTION

[0008] It is a general object of the present invention to provide animproved and useful interlock system in which the above-mentionedproblems are eliminated.

[0009] A more specific object of the present invention is to provide aninterlock system which, when an abnormality occurs in a controller, candiscriminate the controller in which the abnormality occurs in a controlsystem of a semiconductor manufacturing apparatus in which a pluralityof controllers are connected through a network.

[0010] In order to achieve the above-mentioned objects, there isprovided according to the present invention a semiconductormanufacturing apparatus, comprising: a processing system containing atleast one processing chamber which performs a semiconductormanufacturing process; a conveyance system which takes an object to beprocessed in and out of said processing chamber; and a control systemincluding at least one apparatus controller, which controls saidprocessing system and said conveyance system, and an equipmentcontroller, which manages said apparatus controller, said apparatuscontroller and said equipment controller being communicably connectedthrough a network, wherein the apparatus controller and the equipmentcontroller, which are connected via the network, are also connected viaa hard wire so as to transmit a status signal inside the apparatuscontroller and the equipment controller to the control system. Thereby,a presence of each apparatus controller and a status of connectionbetween the controllers can be detected without using communicationthrough the network.

[0011] The semiconductor manufacturing apparatus according to one aspectof the present invention is characterized in that said control systemfurther includes a first path, which transmits a status signal of saidapparatus controller to said equipment controller via a hard wire, and asecond path, which transmits a status signal of said equipmentcontroller to said apparatus controller via a hard wire.

[0012] The first path first path preferably includes a path, whichtransmits a status signal between the apparatus controller and otherapparatus controllers. Thereby, since all apparatus controllers canacquire the status signal of other equipment controllers, each apparatuscontroller can take safety measures in accordance with a status of thecontrol system.

[0013] Additionally, it is preferable that the equipment controllercomprises means for determining whether or not a communicationconnection can be established between the apparatus controllers for afurther process based on the status signal transmitted from theapparatus controller. Thereby, the equipment controller can avoid wasteof time to be generated by trying communication connection between theapparatus controller with which a communication connection cannot beestablished.

[0014] Moreover, it is preferable that the apparatus controllercomprises means for determining contents of a further process based onthe status signal transmitted from the equipment controller. Thereby,the apparatus controller can electively carry out the safe measures atthe time of abnormalities according to the status of the equipmentcontroller or the state of the apparatus controller reflected in thestatus of the equipment controller.

[0015] Additionally, there is provided according to another aspect ofthe present invention a bootstrap method of a control system of asemiconductor manufacturing apparatus comprising: a processing systemcontaining at least one processing chamber which performs asemiconductor manufacturing process; a conveyance system which takes anobject to be processed in and out of said processing chamber; and saidcontrol system including a plurality of apparatus controllers, whichcontrol said processing system and said conveyance system, and anequipment controller, which manages said apparatus controllers, saidapparatus controllers and said equipment controller being communicablyconnected through a network, characterized by comprising: a step ofinitializing said equipment controller; a step of detecting a statussignal of each of said apparatus controllers connected to said equipmentcontroller via a hard wire; a step of identifying an apparatuscontroller, which can load a program, from among said apparatuscontrollers based on the status signals of said apparatus controllers; astep of establishing a communication connection via said network betweensaid equipment controller and said identified apparatus controller; astep of loading a program to be executed to said identified apparatuscontroller from said equipment controller via said network, and startingthe program; a step of detecting the status signal of said identifiedapparatus controller connected to said equipment controller via a hardwire; and a step of determining whether or not said identified apparatuscontroller executed said program based on the status signal of saididentified apparatus controller.

[0016] Thus, by the equipment controller acquiring the status signal ofthe apparatus controller to which the equipment controller is connectedvia the hard wire, the bootstrap can be appropriately and efficientlyperformed in accordance with the configuration of the control system.

[0017] Additionally, there is provided according to further aspect ofthe present invention an interlock method of a control system of asemiconductor manufacturing apparatus comprising: a processing systemcontaining at least one processing chamber which performs asemiconductor manufacturing process; a conveyance system which takes anobject to be processed in and out of said processing chamber; and saidcontrol system including a plurality of apparatus controllers, whichcontrol said processing system and said conveyance system, and anequipment controller, which manages said apparatus controllers, saidapparatus controllers and said equipment controller being communicablyconnected through a network, characterized by comprising: a step ofsetting a status signal representing an abnormality in one of saidapparatus controllers in which the abnormality occurs; a step oftransmitting the status signal representing the abnormality of said oneof said apparatus controllers to said equipment controller connected tosaid one of said apparatus controller via a hard wire; a step oftransmitting the status signal-representing the abnormality from saidequipment controller to all of said apparatus controllers connected tosaid equipment controller via a hard wire; and a step of performing aninterlock operation in each of said apparatus controllers to which thestatus signal representing the abnormality is transmitted from saidequipment controller via the hard wire.

[0018] Accordingly, since the apparatus controller can selectivelyperform the interlock operation when an abnormality is detected in thecontrol system, operators can individually take safety measures inaccordance with a condition such as moving to a safe position, waitingafter returning a position to resume the operation or waiting at aposition where a person can easily access.

[0019] Other objects, features and advantages of the present inventionwill become more apparent from the following detailed description whenread in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

[0020]FIG. 1 is a figure showing a mechanism part of a semiconductormanufacturing apparatus according to a first embodiment of the presentinvention.

[0021]FIG. 2 is an illustrative structure diagram of a control system ofthe semiconductor manufacturing apparatus according to the firstembodiment of the present invention.

[0022]FIG. 3 is a diagram for explaining an interlock unit according toa second embodiment of the present invention.

[0023]FIG. 4 is a diagram for explaining an interlock unit according toa third embodiment of the present invention.

[0024]FIG. 5 is a structure diagram of an equipment controller accordingto a fourth embodiment of the present invention.

[0025]FIG. 6 is a composition figure of an apparatus controlleraccording to a fifth embodiment of the present invention.

[0026]FIG. 7 is a flowchart of a bootstrap method of a control system ofa semiconductor control device according to a sixth embodiment of thepresent invention. operation of this invention of operation.

[0027]FIG. 8 is a sequence chart of an operation according to aninterlock method of a control system of a semiconductor manufacturingapparatus according to a seventh embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

[0028] A description will now be given, with reference to the drawings,of embodiments of the present invention. In the drawings, equivalentparts are given the same reference numerals.

[0029]FIG. 1 is a plan view of a mechanism part of a semiconductormanufacturing apparatus according to a first embodiment of the presentinvention. A description will be given, with reference to FIG. 1, of themulti-chamber semiconductor manufacturing apparatus, especially, acluster tool apparatus 2. The cluster tool apparatus 2 is constituted bya processing system 4, which applies various kinds of processes, such asa film deposition process, a diffusion process or an etching process, toa semiconductor wafer W as an object to be conveyed, and a conveyancesystem 6 which carries the wafer in and out of the processing system 4.

[0030] The processing system 4 comprises a transfer chamber 8, in whicha vacuum can be crated, and four processing chambers 12A-12D connectedto the transfer chamber 8 via respective gate valves 10A-10D. In theprocessing chambers 12A-12D, the same or different kinds of heattreatments are applied to the wafer W. Susceptors 14A-14D, on which thewafer W is placed, are provided in the respective chambers 12A-12D. Atelescopic and pivotable transfer arm part 16 is provided in thetransfer chamber 8. The transfer arm part 16 transfers the wafer betweenthe chambers 12A-12D and a load lock chamber described later.

[0031] The conveyance system 6 comprises a cassette stage 18 on which acassette container is placed and a conveyance stage 22 which moves aconveyance arm part 20 for delivering the wafer W. The cassette stage 24is provided with a container table 24 so that a plurality of cassettecontainers (in this case, four containers at maximum) 26A-26D can beplaced thereon. Each of the cassette containers 26A-26D is constitutedso a maximum of 25 wafers W, for example, can be accommodated at equalpitches.

[0032] A guidance rail 28 extending along the longitudinal direction inthe central part is provided in the conveyance stage 22. Theabove-mentioned conveyance arm part 20 is slidably supported by theguidance rail 28. The guidance rail 28 is provided with a ball screw 30as a moving mechanism in a parallel manner. A base 34 of theabove-mentioned conveyance arm part 20 is fitted to the ball screw 30.Accordingly, the conveyance arm part 20 is movable along the guidancerail 28 by driving a drive motor 32 provided on the end of the ballscrew 30.

[0033] An orienter 36 is provided on the other end of the conveyancestage 22 as a directional positioning device which positions the wafer.Additionally, two load lock chambers 38A and 38B, in which a vacuum canbe formed, are provided in the middle of the conveyance stage 22 so asto connect between the above-mentioned transfer chamber 8. In each ofthe load lock chambers 38A and 38B, a conveyed body tables 40A and 40Bon which the wafer W is placed are provided. Additionally, gate valves42A, 42B and 44A, 44B are provided in front and behind each of the loadlock chambers 38A and 38B, the gate valves for communicating with thetransfer chamber 8 or the conveyance stage 22.

[0034] The above-mentioned conveyance arm part 20 has a telescopic,multi-articulated conveyance arm body 46 and a fork 48 mounted on an endof the arm body 46. The wafer W is held directly on the fork 48.

[0035] The orienter 36 has a rotation reference stand 60, which isrotated by a drive motor. The rotation reference stand 60 rotates whilethe wafer W is placed thereon. An optical sensor 62 for detecting thecircumferential edge of wafer W is provided in the periphery of therotation reference stand 60. Moreover, a level detector is provided onthe side of entrance of the orienter 36, the level detector consistingof a laser element 68 outputting a laser beam 66 for detection of thehorizontal level and a light-receiving element 70 receiving the laserbeam 66.

[0036] The cluster tool apparatus 2 has an apparatus controller (notshown in the figure) which controls operation of the conveyance system.The apparatus controller controls conveyance of wafer W based on theinformation acquired in position information of axis and informationacquired by each detection part

[0037]FIG. 2 is a block diagram of a control system of the semiconductormanufacturing apparatus according to the first embodiment of the presentinvention. The control system comprises: an apparatus controller 121which controls the conveyance system 6; an apparatus controller 122which controls a first processing chamber which performs a singlesemiconductor manufacturing process such as a film deposition process;an apparatus controller 123 which controls a second processing chamberwhich performs a process such as a diffusion process; and apparatuscontrollers corresponding to respective process chambers. Additionally,the control system further comprise an equipment controller 110 whichintegrally manages information on the whole semiconductor manufacturingapparatus, and the equipment controller 110 may be connected to a hostcomputer (not shown in the figure) of the factory in which, for example,the semiconductor manufacturing apparatus is installed.

[0038] The equipment controller 110 and the apparatus controllers 121,122 and 123 are mutually connected through a network, typically a LANtype network 132 such as the Ethernet. The network 132 can beconstituted for example, in a star type. FIG. 2 shows the star typenetwork 132. At this time, the control system has a hub 130 which is aline concentrator, and the equipment controller 110 and the apparatuscontrollers 121, 122 and 123 are connected through the hub 130.

[0039] Programs executed by the apparatus controllers and parametersrelated to the programs are downloaded from the equipment controller 110to each of the apparatus controllers 121, 122 and 123 through a network132. Moreover, the measurement data under processing is uploaded fromeach of the apparatus controllers 121, 122 and 123 to the equipmentcontroller 110.

[0040] Additionally, the control system according to the firstembodiment of the present invention further comprises an interlock unit200. The equipment controller 110 and the apparatus controllers 121, 122and 123 are connected to the interlock unit 200 via a hard wire 202. Theinterlock unit 200 transmits a status signal of the controller throughthe hard wire 202. The status signal of the controller includes, forexample, information indicating whether or not the preparation ofhardware is completed and information indicating whether or not thepreparation of software is completed. If the status signal of thecontroller indicates neither a software-ready state nor a hardware-readystate, this means that the software is not loaded to the controller orthere is a software problem occurring in the controller.

[0041] As mentioned above, since the equipment controller 110 and theapparatus controllers 121, 122 and 123 are connected by the hard wire,and the status signal can be exchanged there between through the hardwire, connection state and operational state of other controllers can bedetected without using communication through the network 132.

[0042] The interlock unit 200 comprises a first path and a second path,the first path transmitting the status signal of the above-mentionedapparatus controllers 121, 122 and 123 to the above-mentioned equipmentcontroller 110 through the hard wire 202, the second path transmittingthe status signal of the above-mentioned equipment controller 110 to theabove-mentioned apparatus controllers 121, 122 and 123 through the hardwire 202.

[0043] Since the equipment controller 110 is able to know the status ofall the apparatus controllers in the control system, the equipmentcontroller 110 can determine its own status signal to be sent to theapparatus controllers based on the status signals received from each ofthe apparatus controllers 121, 122 and 123. The signal supplied to eachof the controllers can be changed by changing the wiring method of thehard wire in the interlock unit 200.

[0044] For example, there is Dizzy chain connection only by the hardwire as an easily realizable form of the interlock unit 200. The Dizzychain connection is an effective connection form, when the connectionorder of the apparatus controllers is fixed.

[0045] Additionally, the interlock unit 200 may receive an interlocksignal from the exterior, and may be constituted to supply the interlocksignal by combining with the status signal to each controller.

[0046]FIG. 3 is a diagram of the interlock unit 200 according to asecond embodiment of the present invention. In the present embodiment,on the equipment controller 110 and two apparatus controllers 121 and122 are shown for the sake of simplification. However, the number of theapparatus controllers is not restricted. The interlock unit 200comprises an interlock board 204 and a connector part 206. The equipmentcontroller 110 and the two apparatus controllers 121 and 122 areconnected by hardwire via the connector part 206 and the interlock board204.

[0047] On the interlock board 204, a signal MC#1_STATUS, a signalMC#2_STATUS and a signal EC_STATUS represent the status signal of thefirst apparatus controller 121, the status signal of the secondapparatus controller 12 e and the status signal of the equipmentcontroller 110, respectively. More specifically, the signal MC#1_STATUSincludes a signal MC#1_HARD_RDY indicating the state of operation of thehardware and a signal MC#1_SOFT_RDY indicating the state of operation ofthe software of the first apparatus controller 121. Similarly, thesignal MC#2_STATUS includes a signal MC#2_HARD_RDY indicating the stateof operation of the hardware and a signal MC#2_SOFT_RDY indicating thestate of operation of the software of the second apparatus controller122.

[0048] On the other hand, the status signal EC_STATUS of the equipmentcontroller 110 includes a signal EC_HARD_RDY indicating the state ofoperation of the hardware of the equipment controller 110, a signalEC_SOFT_RDY indicating the state of operation of the software of theequipment controller 110, and a signal MC_RSTn for forcibly resettingeach apparatus controller. According to such a connection form, thestatus signal from all apparatus controllers is supplied to theequipment controller 110, and the status signal of the equipmentcontroller 110 is supplied to all the apparatus controllers.

[0049]FIG. 4 is a diagram of the interlock unit 200 according to a thirdembodiment of the present invention. In FIG. 4, only the equipmentcontroller 110 and two apparatus controllers 121 and 122 are shown forthe sake of simplification. However, the number of apparatus controllersis not restricted. The interlock unit 200 includes an interlock board214 and a connector part 216, and the equipment controller 110 and thetwo apparatus controllers 121 and 122 are connected by a hard wire viathe interlock board 214 and the connector part 216,

[0050] The meaning of signals shown on the interlock board 214 is thesame as that of the case of the interlock unit according to the secondembodiment of the present invention explained with reference to FIG. 3.In the case of the present embodiment, the equipment controller 110 andall apparatus controllers are connected mutually. Moreover, the statussignal of a certain controller is distributed to all other controllers.That is, the status signal about all other controllers is supplied to acertain controller.

[0051] Thereby, since all apparatus controllers can acquire the statussignals of not only the equipment controller 110 but also otherapparatus controllers, each apparatus controller can selectively performoperation according to the connection state.

[0052]FIG. 5 is a structure diagram of the equipment controller 110according to a fourth embodiment of the present invention. The equipmentcontroller 110 is connected, via the network such as the Ethernet, tothe apparatus controller 121 for the conveyance system, the apparatuscontroller for the first process chamber, and the apparatus controller123 for the second process chamber. The apparatus controller 121 for theconveyance system, the apparatus controller for the first processchamber and the apparatus controller 123 for the second process chamberrespectively control operations of the conveyance system mechanism part6, the process chamber 12A and the process chamber 12B shown in FIG. 1.

[0053] The equipment controller 110 has a memory device 112 such as ahard disk unit, a floppy disk unit or an IC memory unit, and variouskinds of information required for operation of the semiconductormanufacturing apparatus is stored in the memory device 112. That is, thememory device 112 stores, for example, the program for operation of theequipment controller 110, the apparatus operation program executed bythe conveyance system apparatus controller 121 for operating theconveyance system and the corresponding apparatus operation conditionparameters, the apparatus operation program executed by the apparatuscontrollers 122 and 123 for controlling the processes of the processchambers 122 and 123 and the corresponding apparatus operation conditionparameters, the user's specific recipe, and the apparatus log data.

[0054] The equipment controller 110 has a CPU 111 for executing theabove-mentioned programs, and downloads various kinds of informationstored in the memory device 112 to the apparatus controllers 121, 122and 123 through the network 132, or acquires various kinds ofinformation from the apparatus controllers 121, 122 and 123, and storesthe information in a memory 114 or the memory device 112. The equipmentcontroller 110 further includes an input/output device 113 constitutedby a display, a keyboard, etc., and a user can set up and edit variousprograms and parameters which are stored in the above-mentioned memorydevice 112 through the input/output device 113.

[0055] Additionally, according to a fourth embodiment of the presentinvention, the equipment controller 110 comprises an interlock part 115,and judges whether or not communication connection can be establishedfor a further process between the above-mentioned apparatus controllersbased on the status signal of each apparatus controller which istransmitted from the above-mentioned apparatus controllers 121, 122 and123. Thereby, the equipment controller 110 can avoid waste of timecaused by trying establishment of the communication connection betweenthe apparatus controllers which cannot be establish. Moreover, the bootup of the apparatus controllers can be carried out, and theinitialization process of the apparatus controllers which downloads aprogram can be efficiently performed.

[0056]FIG. 6 is a block diagram of an apparatus controller (for example,a conveyance system for a conveyance system) 121 according to a fifthembodiment of the present invention. The apparatus controller 121 has amemory 152 constituted by a flash memory, EPROM, EEROM, etc. The memory152 stores an apparatus control program. Moreover, apparatus operationcondition parameters are developed on the memory 152. A CPU151 controlsthe apparatus by executing the apparatus control program stored in thememory 152 by referring to the execution values of the apparatusoperation condition parameters developed on the memory 152. Theapparatus controller 121 further includes an auxiliary memory device 153constituted by a memory card and a card reader. The auxiliary memorydevice 153 stores information for later use. Moreover, the apparatuscontroller 121 includes a user interface part 155 having an input partand a display part. Through the user interface part 155, a user canissue instructions to the apparatus controller 121, or can see themessage from the apparatus controller 121. Furthermore, the apparatuscontroller 121 includes a communication interface part 156 connected tothe communication network, and can exchange information between theequipment controller 110 and other apparatus controllers 122 and 123.

[0057] According to the fifth embodiment of the present invention, theapparatus controller 121 has an interlock part 157 connected to theinterlock unit 200, and the interlock part 157 judges the contents of afurther process based on the status signal of the equipment controlleracquired from the equipment controller 110 through the interlock unit200. The contents of a further process to be judged may includecontinuation of a process, interruption of a process, restart of aprocess, move to a safe position, immediate stop, etc. Thereby, theapparatus controller 121 can electively take safety measures at the timeof abnormalities according to the state of the equipment controller 110or the state of other apparatus controllers such as the apparatuscontroller 122 which is reflected in the state of the equipmentcontroller 110.

[0058]FIG. 7 is a flowchart of operation according to a bootstrap methodof a control system of a semiconductor manufacturing apparatus accordingto the sixth embodiment of the present invention. The present embodimentis an example which realizes the sequence in which an equipmentcontroller downloads a program for an apparatus controller from theequipment controller after a power is turned on.

[0059] After a power is turned on, the equipment controller initializesthe equipment controller (Step 1). Then, the status signal of theapparatus controller connected to the equipment controller through thehard wire is detected (Step 2). Next, based on the status signal, anapparatus controller, which is in a state in which a program can beloaded, is discriminated from among the apparatus controllers (Step 3).The state in which a program load is possible is equivalent to the statewhere a signal MC_SOFT_RDY indicating an operational state of thehardware in the status signal of the apparatus controller is turned ON,and a signal MC_HARD_RDY indicating an operational state of the softwarein the status signal of the apparatus controller is turned OFF.

[0060] Next, the equipment controller establishes the communicationconnection through a network between the discriminated apparatuscontroller (Step 4). Then the program, which is performed by thediscriminated apparatus controller, is downloaded from the equipmentcontroller to the apparatus controller (Step 5). Then, the programdownloaded to the apparatus controller through the network is performed(Step 6).

[0061] In order to acquire the state of operation of the discriminatedapparatus controller, the equipment controller detects the status signalof the apparatus controller connected through the hard wire (Step 7).Since the communication connection is established between the equipmentcontroller and the apparatus controller in this stage, the equipmentcontroller can also acquire the state of the apparatus controllerthrough the network. However, it is preferable to detect the statussignal through the hard wire from the viewpoint of reducing a processtime.

[0062] Next, it is judged whether or not the apparatus controllernormally executes the downloaded program (Step 8). When the signalMC_SOFT_RDY is ON and the signal MC_HARD_RDY is ON, it is judged thatthe apparatus controller is normally operated according to thedownloaded program.

[0063] When it is judged that the apparatus controller is normallyoperated, the equipment controller advances the process to Step 10 so asto judge whether or not there is an apparatus controller which has notbeen processed (Step 10). When such an apparatus controller stillexists, the process returns to Step 2. When the process is ended aboutall apparatus controllers, the series of sequence is ended.

[0064] On the other hand, if it is judged that the apparatus controllerdoes not normally execute the downloaded program, the signal MC_RST forforcibly resetting is given to the apparatus controller from theequipment controller so as to recover the error state of the apparatuscontroller (Step 9).

[0065] Thus, by acquiring the status signal of the apparatus controllerto which the equipment controller is connected by the hard wireconnection, an equipment controller can download the program for theapparatus controller in the control system, and is able to have theapparatus controller to perform the program. Thereby, a bootstrap can beappropriately and efficiently performed in accordance with theconfiguration of the control system.

[0066]FIG. 8 is a sequence chart of an interlock method of an operationof a control system of a semiconductor manufacture equipment accordingto the seventh embodiment of the present invention. A description willnow be give, with reference to FIG. 8, of a method of interlocking whenan error occurs in a certain apparatus controller.

[0067] First, if software-fault occurs in an apparatus controller, anerror on the software is detected using a well-known technique such as awatch-dog timer. Then, a software ready signal MC_SOFT_RDY of theapparatus controller is changed to OFF (Step 20). This signal istransmitted to the equipment controller through the hard wire.

[0068] The equipment controller detects that it is not ready withrespect to software from the status signal of the apparatus controller(Step 21). Other apparatus controllers are notified that a softwareproblem occurs in the system by the soft ready signal MC_SOFT_RDY of theequipment controller being turned OFF, and a forcible reset signal istransmitted through the hard wire to the apparatus controller in whichthe error occurs (Step 22). The apparatus controller of an errorgeneration source which received the forcible reset signal through thehard wire performs the forcible reset process, and wait for nextinstruction (Step 23).

[0069] On the other hand, upon reception of the status signal of theequipment controller, other apparatus controllers perform, on anindividual controller basis, a suitable risk-aversion process (forexample, stop after going on to a safe place or process), and waits fornext instruction (Step 24). Thereby, high speed and high safetyinterlocking operation using a hard wire can be realized when an erroroccurs.

[0070] It should be noted that, in the present embodiment, when thesoftware error of an apparatus controller is detected, other apparatuscontrollers are notified of the occurrence of the error by changing thestatus signal of the equipment controller. However, for example, if thehard wire connection of the status signal is mutually made for everyapparatus controller, then all apparatus controllers can recognizedirectly the apparatus controller in which the error occurs. As aresult, the risk-aversion process according to the error generationsource can be taken.

[0071] Thereby, since the apparatus controllers can selectively performan interlock operation on an individual controller basis when anabnormality is detected in the control system, safety measures can betaken individually in accordance with a situation, such as moving to asafe place, waiting after returning to a position where a restart can bemade or waiting in a state in which a person can easily access.

[0072] As mentioned above, in the semiconductor manufacturing apparatusaccording to the present invention, the equipment controller and theapparatus controllers, which are connected through the network, are alsoconnected by the hard wire, and the status signal of the apparatuscontrollers and the equipment controller are transmitted to the controlsystem. Thereby, within a control system, the existence and a state ofoperation of each apparatus controller and the connection state betweencontrollers can be detected according to the status signal, withoutusing communication through the network. Therefore, since an abnormalityof the controller or an abnormality of the network can be detectedwithin a time which is not an order of a time (several seconds or somedozens of seconds) required for establishment of the networkcommunication but an order of less than 1 second, an immediate responsecan be taken with respect to an occurrence of the abnormality and arequired measure can be taken. Since the status signal of the equipmentcontroller or all apparatus controllers can be supplied to eachapparatus controller via the hard wire, each apparatus controller canimmediately take safety measures on an individual controller basis.

[0073] The present invention is not limited to the specificallydisclosed embodiments, and variations and modifications may be madewithout departing from the scope of the present invention.

1. A semiconductor manufacturing apparatus, comprising: a processingsystem containing at least one processing chamber which performs asemiconductor manufacturing process; a conveyance system which takes anobject to be processed in and out of said processing chamber; and acontrol system including at least one apparatus controller, whichcontrols said processing system and said conveyance system, and anequipment controller, which manages said apparatus controller, saidapparatus controller and said equipment controller being communicablyconnected through a network, characterized in that: said control systemfurther includes a first path, which transmits a status signal of saidapparatus controller to said equipment controller via a hard wire, and asecond path, which transmits a status signal of said equipmentcontroller to said apparatus controller via a hard wire.
 2. Thesemiconductor manufacturing apparatus as claimed in claim 1,characterized in that said first path includes a path, which transmits astatus signal between said apparatus controller and other apparatuscontrollers.
 3. The semiconductor manufacturing apparatus as claimed inclaim 1 or 2, characterized in that said equipment controller comprisesmeans for determining whether or not a communication connection can beestablished between said apparatus controllers for a further processbased on the status signal transmitted from said apparatus controller.4. The semiconductor manufacturing apparatus as claimed in one of claims1 to 3, characterized in that said apparatus controller comprises meansfor determining contents of a further process based on the status signaltransmitted from said equipment controller.
 5. A bootstrap method of acontrol system of a semiconductor manufacturing apparatus comprising: aprocessing system containing at least one processing chamber whichperforms a semiconductor manufacturing process; a conveyance systemwhich takes an object to be processed in and out of said processingchamber; and said control system including a plurality of apparatuscontrollers, which control said processing system and said conveyancesystem, and an equipment controller, which manages said apparatuscontrollers, said apparatus controllers and said equipment controllerbeing communicably connected through a network, characterized bycomprising: a step of initializing said equipment controller; a step ofdetecting a status signal of each of said apparatus controllersconnected to said equipment controller via a hard wire; a step ofidentifying an apparatus controller, which can load a program, fromamong said apparatus controllers based on the status signals of saidapparatus controllers; a step of establishing a communication connectionvia said network between said equipment controller and said identifiedapparatus controller; a step of loading a program to be executed to saididentified apparatus controller from said equipment controller via saidnetwork, and starting the program; a step of detecting the status signalof said identified apparatus controller connected to said equipmentcontroller via a hard wire; and a step of determining whether or notsaid identified apparatus controller executed said program based on thestatus signal of said identified apparatus controller.
 6. An interlockmethod of a control system of a semiconductor manufacturing apparatuscomprising: a processing system containing at least one processingchamber which performs a semiconductor manufacturing process; aconveyance system which takes an object to be processed in and out ofsaid processing chamber; and said control system including a pluralityof apparatus controllers, which control said processing system and saidconveyance system, and an equipment controller, which manages saidapparatus controllers, said apparatus controllers and said equipmentcontroller being communicably connected through a network, characterizedby comprising: a step of setting a status signal representing anabnormality in one of said apparatus controllers in which theabnormality occurs; a step of transmitting the status signalrepresenting the abnormality of said one of said apparatus controllersto said equipment controller connected to said one of said apparatuscontroller via a hard wire; a step of transmitting the status signalrepresenting the abnormality from said equipment controller to all ofsaid apparatus controllers connected to said equipment controller via ahard wire; and a step of performing an interlock operation in each ofsaid apparatus controllers to which the status signal representing theabnormality is transmitted from said equipment controller via the hardwire.